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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge
1.0 Features (CY7C68300B/CY7C68301B and CY7C68320/CY7C68321)
* Support for CompactFlash and one ATA/ATAPI device * Can place the ATA interface in high-impedance (Hi-Z) to allow sharing of the ATA bus with another controller (e.g., an IEEE-1394 to ATA bridge chip or MP3 Decoder) * Support for board-level manufacturing test via USB interface * Low-power 3.3V operation * Fully compatible with native USB mass storage class drivers * Cypress mass storage class drivers available for Windows (98SE, ME, 2000, XP) and Mac OS X
* Fixed-function mass storage device--requires no firmware code * Two power modes: Self-powered and USB bus-powered to enable bus powered CF readers and truly portable USB hard drives * Certified compliant for USB 2.0 (TID# 40460273), the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport (BOT) Specification * Operates at high (480-Mbps) or full (12-Mbps) speed USB * Complies with ATA/ATAPI-6 specification * Supports 48-bit addressing for large hard drives * Supports ATA security features * Supports all ATA commands via ATACB function * Supports mode page 5 for BIOS boot support * Supports ATAPI serial number VPD page retrieval for Digital Rights Management (DRM) compatibility * Supports PIO modes 0, 3, 4, multiword DMA mode 2, and UDMA modes 2, 3, 4 * Uses one external serial EEPROM for storage of USB descriptors and device configuration data * ATA interface IRQ signal support * Support for one or two ATA/ATAPI devices
1.1
Features (CY7C68320/CY7C68321 only)
* Supports HID interface or custom GPIOs to enable features such as single button backup, power-off, LED-based notification, etc. * Lead-free 56-pin QFN and 100-pin TQFP packages * CY7C68321 is ideal for battery-powered designs * CY7C68320 is ideal for self- and bus-powered designs
1.2
Features (CY7C68300B/CY7C68301B only)
* Pin-compatible with CY7C68300A (using Backward Compatibility mode) * Lead-free 56-pin SSOP and 56-pin QFN packages * CY7C68301B is ideal for battery-powered designs * CY7C68300B is ideal for self- and bus-powered designs
2.0
Block Diagram
SCL RESET I2C Bus Controller SDA
Misc control signals 24 MHz XTAL PLL
ATA_EN (ATA Interface 3-state)
Internal Control Logic
ATA Interface Control Signals
Control ATA Interface Logic
16 Bit ATA Data
VBUS D+ D-
USB 2.0 XCVR
CY Smart USB FS/HS Engine
4kByte FIFO
Data
Figure 2-1. Block Diagram Cypress Semiconductor Corporation Document 38-08033 Rev. *D * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised February 21, 2005
CY7C68300B/CY7C68301B CY7C68320/CY7C68321
3.0 Applications
mass storage device ports. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification and is intended for bus- and self-powered devices. The AT2LP is the latest addition to the Cypress USB mass storage portfolio, and is an ideal cost- and power-reduction path for designs that previously used the ISD-300A1, ISD300LP, or EZ-USB AT2. Specifically, the CY7C68300B/CY7C68301B includes a mode that makes it pin-for-pin compatible with the EZUSB AT2 (CY7C68300A). The USB port of the CY7C68300B/301B and CY7C68320/321 (AT2LP) are connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the AT2LP and receives status and data from the AT2LP using standard USB protocol. The ATA/ATAPI port of the AT2LP is connected to one or two mass storage devices. A 4-Kbyte buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, multiword DMA mode 2 and Ultra DMA modes 2, 3, and 4. The device initialization process is configurable, enabling the AT2LP to initialize ATA/ATAPI devices without software intervention.
The CY7C68300B/301B and CY7C68320/321 implement a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage devices, such as the following. * Hard drives * CD-ROM, CD-R/W * DVD-ROM, DVD-RAM, DVD+/-R/W * MP3 players * Personal media players * CompactFlash * Microdrives * Tape drives * Personal video recorders The CY7C68300B/301B and CY7C68320/321 support one or two devices in the following configurations. * ATA/ATAPI master only * ATA/ATAPI slave only * ATA/ATAPI master and slave * CompactFlash only * ATA/ATAPI slave and CompactFlash or other removable IDE master
3.1
* * * *
Additional Resources
CY4615B EZ-USB AT2LP Reference Design Kit USB Specification version 2.0 ATA Specification T13/1410D Rev 3B USB Mass Storage Class Bulk Only Transport Specification, www.usb.org
5.0
68300A Compatibility
4.0
Introduction
The EZ-USB AT2LPTM (CY7C68300B/CY7C68301B and CY7C68320/CY7C68321) implements a fixed function bridge between one USB port and one or two ATA- or ATAPI-based
Read EEPROM
The CY7C68300B/301B and CY7C68320/321 are available in three package types that are pictured in the following sections. As mentioned above, the CY7C68300B/301B contains a backward compatibility mode that allows the CY7C68300B/301B to be used in existing EZ-USB AT2 (CY7C68300A) designs. Please refer to the logic flow below for more information on the pinout selection process.
EEPROM Signature 0x4D4D?
No
Yes Set EZ-USB AT2 (CY7C68300A) Pinout Set EZ-USB AT2LP (CY7C68300B) Pinout
Normal Operation
Figure 5-1. Simplified Startup Flowchart (68300B only)
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
5.1 Pin Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
DD13 DD14 DD15 GND ATAPUEN (GND) VCC GND IORDY DMARQ AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND
DD12 DD11 DD10 DD9 DD8 (ATA_EN) VBUS_ATA_ENABLE VCC RESET# GND ARESET# (VBUS_PWR_VALID ) DA2 CS1# CS0# (DA2) DRVPWRVLD
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
EZ-USB AT2LP CY7C68300B CY7C68301B 56-pin SSOP
DA1 DA0 INTRQ VCC DMACK# DIOR# DIOW# GND VCC
PWR500# ( PU 10K) GND ( Reserved) SCL SDA VCC DD0 DD1 DD2 DD3
NOTE: Labels in italics denote pin functionality during CY7C68300A compatibility mode.
GND DD7 DD6 DD5 DD4
Figure 5-2. 56-pin SSOP Pinout (CY7C68300B/CY7C68301B only)
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
VBUS_ATA_ENABLE ( ATA_EN) 44
ATAPUEN (NC)
DD15
DD14
DD13
DD12
DD11
DD10
GND
GND
VCC
56
55
54
53
52
51
50
49
48
47
46
45
IORDY DMARQ AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND
1 2 3 4 5 6 7 8 9 10 11 12
NOTE: Italic labels denote pin functionality during CY7C68300A compatibility mode.
43 42 RESET# 41 GND 40 ARESET# 39 DA2 ( VBUS_PWR_VALID) 38 CS1# 37 CS0# 36 DRVPWRVLD (DA2 ) 35 DA1 34 DA0 33 INTRQ 32 VCC 31 DMACK# 30 DIOR# 29 DIOW# GND 28
EZ-USB AT2LP CY7C68300B CY7C68301B 56-pin QFN
(PU 10K) PWR500# 13 GND 14
15
SDA 16
17
DD0 18
DD1 19
DD2 20
DD3 21
DD4 22
DD5 23
DD6 24
DD7 25
26 GND
SCL
VCC
Figure 5-3. 56-pin QFN Pinout (CY7C68300B/CY7C68301B)
Document 38-08033 Rev. *D
VCC
27
VCC
DD9
DD8
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
VBUS_ATA_ENABLE 44
GPIO2
DD15
DD14
DD13
DD12
DD11
DD10
GND
GND
VCC
56
55
54
53
52
51
50
49
48
47
46
45
IORDY DMARQ AVCC XTALOUT XTALIN AGND VCC DPLUS DMINUS GND VCC GND GPIO1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DD0 18 DD1 19 DD2 20 DD3 21 DD4 22 DD5 23 DD6 24 DD7 25 26 27 28
43 42 41 40 39
VCC
DD9
DD8
RESET# GND ARESET# DA2 CS1# CS0# GPIO0 DA1 DA0 INTRQ VCC DMACK# DIOR# DIOW#
EZ-USB AT2LP CY7C68320 CY7C68321 56-pin QFN
38 37 36 35 34 33 32 31 30 29
SDA
GND
Figure 5-4. 56-pin QFN Pinout (CY7C68320/CY7C68321)
Document 38-08033 Rev. *D
GND
SCL
VCC
VCC
Page 5 of 36
CY7C68300B/CY7C68301B CY7C68320/CY7C68321
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
ATAPUEN GND DD15 DD14 DD13 DD12 GND GPIO5 GPIO4 GPIO3 GPIO2 GPIO1
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VCC GND IORDY DMARQ GND GND GND GND AVCC XTALOUT XTALIN AGND NC NC NC VCC DPLUS DMINUS GND VCC GND SYSIRQ GND GND GND PWR500# GND NC SCL SDA
GPIO0 NC NC VCC GND DD11 DD10 DD9 DD8 VBUS_ATA_ENABLE VCC RESET# NC GND ARESET# DA2 CS1# CS0# DRVPWRVLD DA1 DA0 INTRQ VCC GND NC NC VBUSPWRD NC NC NC LOWPWR# NC DMACK# DIOR# DIOW# VCC NC NC
81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
EZ-USB AT2LP CY7C68320B CY7C68321B 100-pin TQFP
NC NC VCC DD0 DD1 DD2 DD3 VCC GND NC GND NC
31 32 33 34 35 36 37 38 39 40 41 42
43
44
45
46
47
48
49
Figure 5-5. 100-pin TQFP Pinout (CY7C68320/CY7C68321 only)
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50
GND DD4 DD5 DD6 DD7 GND VCC GND
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
5.2 Pin Descriptions
between the 68300B/01B and 68320/321 pinouts for the 56pin packages. For information on the CY7C68300A pinout, please refer to the CY7C68300A data sheet that is found in the "EZ-USB AT2" folder of the CY4615B reference design kit CD.
The following table lists the pinouts for the 56-pin SSOP, 56pin QFN and 100-pin TQFP package options for the AT2LP. Please refer to the Pin Diagrams in section 5.1 for differences
Table 5-1. AT2LP Pin Descriptions Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode) 56 SSOP 1 2 3 4 5 56 QFN 50 51 52 53 54[3] 100 TQFP 96 97 98 99 100[3] Pin Name DD13 DD14 DD15 GND ATAPUEN (NC) Pin Default State Type at Start-up Pin Description I/O[1] Hi-Z ATA Data bit 13. I/O[1] I/O[1] GND I/O Hi-Z Hi-Z ATA Data bit 14. ATA Data bit 15. Ground. ATA pull-up voltage source for bus-powered applications (see section 5.3.10). Alternate Function: Input when the EEPROM configuration byte 8 has bit 7 set to one. The input value is reported through EP1IN (byte 0, bit 2). VCC. Connect to 3.3V power source. Input Input Ground. ATA Control. ATA Control. Ground.
6 7 8 9 N/A
55 56 1 2 N/A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26[3]
VCC GND IORDY DMARQ GND
PWR GND I[1] I[1]
10 11 12 13 N/A
3 4 5 6 N/A
AVCC XTALOUT XTALIN AGND NC
PWR Xtal Xtal GND Xtal Xtal
Analog VCC. Connect to VCC through the shortest path possible. 24-MHz Crystal Output (see section 5.3.3). 24-MHz Crystal Input (see section 5.3.3). Analog Ground. Connect to ground with as short a path as possible. No Connect.
14 15 16 17 18 19 N/A N/A
7 8 9 10 11 12 N/A N/A
VCC DPLUS DMINUS GND VCC GND SYSIRQ GND
PWR I/O I/O GND PWR GND I GND
Hi-Z Hi-Z
VCC. Connect to 3.3V power source. USB D+ Signal (see section 5.3.1). USB D- Signal (see section 5.3.1). Ground. VCC. Connect to 3.3V power source. Ground.
Input
Active HIGH. USB interrupt request (see section 5.3.4). Tie to GND if functionality is not used. Ground.
20
13[3]
PWR500#[2] (PU 10K) GND (RESERVED)
I/O
Active LOW. VBUS power granted indicator used in bus-powered designs (see section 5.3.11). Alternate Function for 68320. Reserved. Tie to GND.
21
14
27
Notes: 1. If byte 8, bit 4 of the EEPROM is set to `0', the ATA interface pins are only active when VBUS_ATA_EN is asserted. See section 5.3.9. 2. A `#' sign after the pin name indicates that it is active LOW. 3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321.
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
Table 5-1. AT2LP Pin Descriptions Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode) (continued) 56 SSOP N/A 22 23 N/A 24 25 26 27 28 N/A N/A N/A N/A N/A N/A 29 30 31 32 33 34 35 N/A N/A 36 37 38 N/A N/A 56 QFN N/A 15 16 N/A 17 18 19 20 21 N/A N/A N/A N/A N/A N/A 22 23 24 25 26 27 28 N/A N/A 29 30 31 N/A N/A 100 TQFP 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pin Name NC SCL SDA NC VCC DD0 DD1 DD2 DD3 VCC GND NC GND NC GND DD4 DD5 DD6 DD7 GND VCC GND NC VCC DIOW#[2] DIOR# DMACK# NC LOWPWR# PWR I/O[1] I/O[1] I/O[1] I/O[1] PWR GND NC NC I/O[1] I/O[1] I/O[1] I/O[1] GND PWR GND NC Hi-Z Hi-Z Hi-Z Hi-Z Pin Default State Type at Start-up No Connect. O I/O Active for Clock signal for I2C interface (see section 5.3.2). several ms at Data signal for I2C interface (see section 5.3.2). start-up. No Connect. VCC. Connect to 3.3V power source. ATA Data bit 0. ATA Data bit 1. ATA Data bit 2. ATA Data bit 3. VCC. Connect to 3.3V power source. Ground. No Connect. Ground. No Connect. Ground. ATA Data bit 4. ATA Data bit 5. ATA Data bit 6. ATA Data bit 7. Ground. VCC. Connect to 3.3V power source. Ground. No Connect. Pin Description
Hi-Z Hi-Z Hi-Z Hi-Z
PWR VCC. Connect to 3.3V power source. O/Z[1] Driven HIGH ATA Control. (CMOS) O/Z[1] Driven HIGH ATA Control. (CMOS) O/Z[1] Driven HIGH ATA Control. (CMOS) NC O No Connect. USB suspend indicator (see section 5.3.7). `0' = Chip active. VBUS power draw governed by PWR500# pin. `Hi-Z' = Chip suspend. VBUS system current limited to USB suspend mode value. No Connect.
N/A
N/A
N/A
N/A
59 60 61 62
NC
NC
VBUSPWRD
I
Input
N/A N/A
N/A N/A
63 64 65
NC GND
NC GND
Bus-powered operation selector. Used in systems that are capable of being bus or self-powered to indicate the current power mode. No Connect. Ground.
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
Table 5-1. AT2LP Pin Descriptions Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode) (continued) 56 SSOP 39 40 41 56 QFN 32 33 34 100 TQFP 66 67 68 Pin Name VCC INTRQ DA0 Pin Default State Type at Start-up Pin Description PWR VCC. Connect to 3.3V power source. I[1] Input O/Z[1] Driven HIGH after 2 ms delay [1] O/Z Driven HIGH after 2 ms delay I Input ATA Interrupt request. ATA Address.
42
35
69
DA1
ATA Address.
43
36[3]
70[3]
DRVPWRVLD (DA2)
Device Presence Detect (see section 5.3.5). Configurable polarity, controlled by EEPROM address 0x08. This pin must be connected to GND if functionality is not utilized. Alternate Function: Input when the EEPROM configuration byte 8 has bit 7 set to one. The input value is reported through EP1IN (byte 0, bit 0).
44
37
71
45
38
72
46
39
73
O/Z[1] Driven HIGH ATA Chip Select. after 2 ms delay CS1# O/Z[1] Driven HIGH ATA Chip Select. after 2 ms delay [1] Driven HIGH ATA Address. DA2 O/Z (VBUS_PWR_VALID) after 2 ms delay CS0# ARESET# GND NC RESET# O/Z[1] GND NC I Input ATA Reset. Ground. No Connect. Chip Reset (see section 5.3.13). This pin is normally tied to VCC through a 100K resistor, and to GND through a 0.1-F capacitor, supplying a 10-ms reset. VCC. Connect to 3.3V power source. VBUS detection (see section 5.3.9). Indicates to the CY7C68300B/CY7C68301B that VBUS power is present. ATA Data bit 8. ATA Data bit 9. ATA Data bit 10. ATA Data bit 11. Ground. VCC. Connect to 3.3V power source. No Connect. General purpose I/O pins (see section 5.3.6). The GPIO pins must be tied to GND if functionality is not utilized. If the hs_indicator config bit is set, the GPIO2_nHS pin will reflect the operating speed: `1' = full-speed operation. `0' = high-speed operation. Hi-Z Ground. ATA Data bit 12.
47 48 N/A 49
40 41 N/A 42
74 75 76 77
50 51
43 44
78 79
VCC VBUS_ATA_ENABLE (ATA_EN) DD8 DD9 DD10 DD11 GND VCC NC GPIO0 GPIO1 GPIO2_nHS GPIO3 GPIO4 GPIO5 GND DD12
PWR I Input
52 53 54 55 N/A N/A N/A N/A
45 46 47 48 N/A N/A N/A 36[3] 13[3] 54[3]
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
I/O[1] I/O[1] I/O[1] I/O[1] PWR NC I/O[3]
Hi-Z Hi-Z Hi-Z Hi-Z
N/A 56
N/A 49
GND I/O[1]
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
5.3
5.3.1
Additional Pin Descriptions
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins; they should be tied to the D+ and D- pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB. See section 15.0 for PCB layout recommendations. When RESET# is released, the internal pull-up on D+ is controlled by VBUS_ATA_ENABLE. When VBUS_ATA_ENABLE is HIGH, D+ is pulled up. 5.3.2 SCL, SDA
resonant fundamental mode) crystal is used, but a 24-MHz square wave from another source can also be used. If a crystal is used, connect its pins to XTALIN and XTALOUT, and also through 12-pF capacitors to GND as shown in Figure 5-6. If an alternate clock source is used, apply it to XTALIN and leave XTALOUT open. 5.3.4 SYSIRQ
The clock and data pins for the I2C port should be connected to the configuration EEPROM and to 2.2K pull-up resistors tied to VCC. The SCL and SDA pins are active for several milliseconds at start-up. 5.3.3 XTALIN, XTALOUT
The SYSIRQ pin provides a way for systems to request service from host software by using the USB Interrupt pipe. If the AT2LP has no pending interrupt data to return, USB interrupt pipe data requests are NAKed. If pending data is available, the AT2LP returns 16 bits of data; this data indicates the HS_MODE signal (that indicates whether AT2LP is operating in high-speed or full-speed), the VBUSPWRD pin, and the GPIO pins. Table 5-2 gives the bitmap for the data returned on the interrupt pipe and Figure 5-7 depicts the latching algorithm incorporated by AT2LP. The SYSIRQ pin must be tied low if the HID function is used (refer to Section 6.0).
The AT2LP requires a 24-MHz (100ppm) signal to derive internal timing. Typically, a 24-MHz (20-pF, 500-W, parallel-
24MHz Xtal
12pF 12pF
XTALIN
XTALOUT
Figure 5-6. XTALIN / XTALOUT Diagram
Table 5-2. USB Interrupt Pipe Data Bitmap USB Interrupt Data Byte 1 7 RESERVED 6 RESERVED 5 RESERVED 4 RESERVED 3 RESERVED 2 RESERVED 1 USB High-Speed 0 VBUSPWRD 7 RESERVED 6 RESERVED USB Interrupt Data Byte 0 5 4 3 2 1 0
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
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GPIO[0]
CY7C68300B/CY7C68301B CY7C68320/CY7C68321
No
No
USB Interrupt Pipe Polled?
SYSIRQ=1?
Yes Yes Int_Data = 1? No
Yes Latch State of IO Pins Set Int_Data = 1
No NAK Request Yes Int_Data = 0 and SYSIRQ=0? Return Interrupt Data Set Int_Data = 0
Figure 5-7. SYSIRQ Latching Algorithm 5.3.5 DRVPWRVLD * The status of the GPIO pins is also returned on the interrupt endpoint (EP1) in response to a SYSIRQ. See section 5.3.3 for SYSIRQ details. GPIO2_nHS also has an alternate function. If the "HS Indicator Enable" configuration (bit 2 of EEPROM address 8) is set, the GPIO2_nHS pin will reflect the operating speed of the device (full- or high-speed USB). 5.3.7 LOWPWR#
When this pin is enabled via EEPROM byte 8, bit 0, the AT2LP will inform the host that a removable device, such as a CF card, is present. The CY7C68300B/CY7C68301B will use DRVPWRVLD to detect that the removable device is present. Pin polarity is controlled by bit 1 of EEPROM address 8. When DRVPWRVLD is deasserted, the AT2LP will report a "no media present" status (ASC = 0x3A, ASQ = 0x00) to the host. When the media has been detected again, the AT2LP will report a "media changed" status to the host (ASC = 0x28, ASQ = 0x00). When a removable device is used, it is always the master device. Only one removable device may be attached to the AT2LP. If the system only contains a removable device, EEPROM byte 8, bit 6 must be set to `0' to disable ATA device detection at start-up. If a non-removable device is connected in addition to a removable media device, it must be configured as a slave (device address 1). DRVPWRVLD can also be configured as an input. See Section 6.0 HID Functions for Button Controls. 5.3.6 GPIO Pins
LOWPWR# is an output pin that is driven to `0' when the AT2LP is active. LOWPWR# is placed in Hi-Z when the AT2LP is in a suspend state. 5.3.8 ATA Interface Pins
Design practices for signal integrity as outlined in the ATA/ATAPI-6 Specification should be followed with systems that utilize a ribbon cable interconnect between the CY7C68300B/CY7C68301B's ATA interface and the attached ATA/ATAPI device, especially if Ultra DMA Mode is utilized. 5.3.9 VBUS_ATA_ENABLE
The GPIO pins allow for a general purpose Input/Output interface. There are several different interfaces to the GPIO pins: * Configuration bytes 0x09 and 0x0A contain the default settings for the GPIO pins. * The host can modify the settings of the GPIO pins during operation. This is done with vendor-specific commands described in Section 8.6.
VBUS_ATA_ENABLE is typically used to indicate to the AT2LP that power is present on VBUS. This pin is polled by the AT2LP at start-up and then every 20ms thereafter. If this pin is `1', the internal 1.5K pull-up is attached to D+. If this pin is `0', the AT2LP will release the pull-up on D+ as required by the USB specification. Also, If EEPROM byte 8, bit 4 is `0', the ATA interface pins will be placed in a high impedance (Hi-Z) state when VBUS_ATA_ENABLE is `0'. If EEPROM byte 8, bit 4 is `1', the ATA interface pins will still be driven when VBUS_ATA_ENABLE is `0'. Page 11 of 36
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CY7C68300B/CY7C68301B CY7C68320/CY7C68321
5.3.10 ATAPUEN 5.3.13 RESET# This output controls the required host pull-up resistors on the ATA interface. ATAPUEN is driven to `0' when the ATA bus is inactive. ATAPUEN is driven to `1' when the ATA bus is active. ATAPUEN is set to a Hi-Z state along with all other ATA interface pins if VBUS_ATA_ENABLE is deasserted and the ATA_EN functionality (EEPROM byte 8, bit 4) is enabled. ATAPUEN can also be configured as an input. See Section 6.0 HID Functions for Button Controls 5.3.11 PWR500#
0.1F
Asserting RESET# for 10 ms will reset the entire chip. This pin is normally tied to VCC through a 100k resistor, and to GND through a 0.1-F capacitor, as shown in the figure below.
100K RESET#
The AT2LP asserts PWR500# to indicate that VBUS current may be drawn up to the limit specified by the bMaxPower field of the USB configuration descriptors. In the 100-pin package, PWR500# will only be asserted if VBUSPWRD and DRVPWRVLD are also asserted. In the 56-pin package, PWR500# only functions during bus-powered operation. If the AT2LP enters a low-power state, PWR500# is deasserted. When normal operation is resumed, PWR500# is restored accordingly. Naturally, the PWR500# pin should never be used to control power sources for the AT2LP. In the 68320 parts, PWR500# can also be configured as an input. If the Drive Power Valid Enable bit is set (EEPROM byte 8, bit 1), PWR500# will ONLY be driven when Drive Power Valid is active. See Section 6.0 HID Functions for Button Controls. 5.3.12 VBUSPWRD
Figure 5-8. Typical Reset Circuit Cypress does not recommend an RC reset circuit for buspowered devices. See the application note EZ-USB FX2TM/AT2TM/SX2TM Reset and Power Considerations at www.cypress.com for more information.
6.0
HID Functions for Button Controls
Some devices have the ability to be either self-powered or bus-powered. The VBUSPWRD input pin enables these devices to change between self-powered to bus-powered modes by changing the contents of the bMaxPower field and the self-powered bit in the configuration descriptor. Note that current host drivers do not poll the device for this information, so this pin is only effective on a USB or power-up reset. Table 5-3. Bus-Power Description VBUSPWRD value PWR500# bMaxPower bmAttributes bit 6 1 1 when Config = 0 0 when Config = 1 250 (500mA) 0 0 1 Not present (56-pin) 1 when Config = 0 0 when Config = 1
Cypress' CY7C68320/CY7C68321 introduces the capability to support Human Interface Device (HID) signaling to the host for such functions as buttons. The ability to add buttons to a mass storage solution opens new applications for backup and other device-side notification to the host. Optional HID functions can be added to the EEPROM descriptors by setting bit 7 of byte 8 of the EEPROM to a value of `1'. When this bit is set, several pins adopt alternate functions for the 56-pin package. This allows the pins to be used as button inputs. If there is a HID descriptor in the EEPROM, these pins are polled by the hardware approximately every 17 ms. If a change is detected in the pin(s) state, a report is sent via EP1. The report format for byte 0 and byte 1 are shown in Table 6-1.
1 (2mA) EEPROM value used 1 EEPROM value used
Table 6-1. EP1 Data Bitmap EP1 Data Byte 1 7 RESERVED 6 RESERVED 5 RESERVED 4 RESERVED 3 RESERVED 2 RESERVED 1 USB High-Speed 0 VBUSPWRD 7 DRVPWRVLD 6 5 EP1 Data Byte 0 4 3 2 1 ATAPUEN 0 PWR500#
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
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7.0
7.1
Functional Overview
USB Signaling Speed
ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class BOT drivers. 7.2.1 ATA Command Block (ATACB)
AT2LP operates at the following two of the three rates defined in the USB Specification Revision 2.0 dated April 27, 2000: * Full-speed, with a signaling bit rate of 12 Mbits/sec * High-speed, with a signaling bit rate of 480 Mbits/sec. AT2LP does not support the low-speed signaling rate of 1.5 Mbits/sec.
7.2
ATA Interface
The ATA/ATAPI port on the AT2LP is compatible with the Information Technology-AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification, T13/1410D Rev 2a. The AT2LP supports both ATAPI packet commands as well as ATA commands (by use of ATA Command Blocks), as outlined in Section 7.2.1. Refer to the USB Mass Storage Class (MSC) Bulk Only Transport (BOT) Specification for information on Command Block formatting. Additionally, the AT2LP translates Table 7-1. ATACB Field Descriptions Byte 0 Field Name bVSCBSignature
The ATA Command Block (ATACB) functionality provides a means of passing ATA commands and ATA register accesses to the attached device for execution. ATACB commands are transferred in the Command Block Wrapper Command Block (CBWCB) portion of the Command Block Wrapper (CBW). The ATACB is distinguished from other command blocks by having the first two bytes of the command block match the bVSCBSignature and bVSCBSubCommand values that are defined in Table 7-1. Only command blocks that have a valid bVSCBSignature and bVSCBSubCommand are interpreted as ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB remain as defined in the USB Mass Storage Class Bulk-Only Transport Specification. The ATACB must be 16 bytes in length. The following table and text defines the fields of the ATACB.
Field Description This field indicates to the CY7C68300B/CY7C68301B that the ATACB contains a vendor-specific command block. This value of this field must match the value in EEPROM address 0x04 for this vendor-specific command to be recognized. This field must be set to 0x24 for ATACB commands. This field controls the execution of the ATACB according to the bitfield values: Bit 7 IdentifyPacketDevice - This bit indicates that the data phase of the command will contain ATAPI (0xA1) or ATA (0xEC) IDENTIFY device data. Setting IdentifyPacketDevice when the data phase does not contain IDENTIFY device data will result in unspecified device behavior. 0 = Data phase does not contain IDENTIFY device data 1 = Data phase contains ATAPI or ATA IDENTIFY device data Bit 6 UDMACommand - This bit enables supported UDMA device transfers. Setting this bit when a non-UDMA capable device is attached will result in undetermined behavior. 0 = Do not use UDMA device transfers (only use PIO mode) 1 = Use UDMA device transfers Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken from the value assigned to the LUN during start-up or from the ATACB. 0 = The DEV bit will be taken from the value assigned to the LUN during start-up 1 = The DEV bit will be taken from the ATACB field 0x0B, bit 4 Bit 4 DErrorOverride - This bit controls the device error override feature. This bit should not be set during a bmATACBActionSelect TaskFileRead. 0 = Data accesses are halted if a device error is detected 1 = Data accesses are not halted if a device error is detected Bit 3 PErrorOverride - This bit controls the phase error override feature. This bit should not be set during a bmATACBActionSelect TaskFileRead. 0 = Data accesses are halted if a phase error is detected 1 = Data accesses are not halted if a phase error is detected Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate Status register will be polled and the BSY bit will be used to qualify the ATACB operation. 0 = The AltStat register will be polled until BSY=0 before proceeding with the ATACB operation 1 = The ATACB operation will be executed without polling the AltStat register.
1 2
bVSCBSubCommand bmATACBActionSelect
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Table 7-1. ATACB Field Descriptions (continued) Byte Field Name Field Description Bit 1 DeviceSelectionOverride - This bit determines when the device selection will be performed in relation to the command register write accesses. 0 = Device selection will be performed prior to command register write accesses 1 = Device selection will be performed following command register write accesses Bit 0 TaskFileRead - This bit determines whether or not the taskfile register data selected in bmATACBRegisterSelect is returned. If this bit is set, the dCBWDataTransferLength field must be set to 8. 0 = Execute ATACB command and data transfer (if any) 1 = Only read taskfile registers selected in bmATACBRegisterSelect and return 0x00h for all others. The format of the 12 bytes of returned data is as follows: * Address offset 0x00 (0x3F6) - Alternate Status * Address offset 0x01 (0x1F1) - Features / Error * Address offset 0x02 (0x1F2) - Sector Count * Address offset 0x03 (0x1F3) - Sector Number * Address offset 0x04 (0x1F4) - Cylinder Low * Address offset 0x05 (0x1F5) - Cylinder High * Address offset 0x06 (0x1F6) - Device / Head * Address offset 0x07 (0x1F7) - Command / Status 3 bmATACBRegisterSelect This field controls which of the taskfile register read or write accesses occur. Taskfile read data will always be 8 bytes in length, and unselected register data will be returned as 0x00. Register accesses occur in sequential order as outlined below (0 to 7). Bit 0 (0x3F6) Device Control / Alternate Status Bit 1 (0x1F1) Features / Error Bit 2 (0x1F2) Sector Count Bit 3 (0x1F3) Sector Number Bit 4 (0x1F4) Cylinder Low Bit 5 (0x1F5) Cylinder High Bit 6 (0x1F6) Device / Head Bit 7 (0x1F7) Command / Status 4 bATACBTransferBlockCount This value indicates the maximum requested block size in 512-byte increments. This value must be set to the last value used for the "Sectors per block" in the SET_MULTIPLE_MODE command. Legal values are 0, 1, 2, 4, 8, 16, 32, 64, and 128 where 0 indicates 256 sectors per block. A command failed status will be returned if an illegal value is used in the ATACB. These bytes contain ATA register data used with ATA command or PIO write operations. Only registers selected in bmATACBRegisterSelect are required to hold valid data when accessed. The registers are as follows. ATACB Address Offset 0x05 (0x3F6) - Device Control ATACB Address Offset 0x06 (0x1F1) - Features ATACB Address Offset 0x07 (0x1F2) - Sector Count ATACB Address Offset 0x08 (0x1F3) - Sector Number ATACB Address Offset 0x09 (0x1F4) - Cylinder Low ATACB Address Offset 0x0A (0x1F5) - Cylinder High ATACB Address Offset 0x0B (0x1F6) - Device ATACB Address Offset 0x0C (0x1F7) - Command 13-15 Reserved These bytes must be set to 0x00 for ATACB commands.
5-12
bATACBTaskFileWriteData
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8.0 Operating Modes
Read EEPROM
EEPROM Found?
No
"No EEPROM Detected" Mode
Yes
EEPROM Signature 0x4D4D?
No
EEPROM Signature 0x534B?
Yes Set EZ-USB AT2+ (CY7C68300A) Pinout
Yes
Set EZ-USB AT2LP Pinout No
ATA Enable Pin HIGH? No Yes No ARESET# LOW? Normal Mass Storage Mode
Yes
Board Manufacturing Test Mode
Figure 8-1. Operational Mode Selection
8.1
Operational Mode Selection Flow
During the power-up sequence, the AT2LP checks the I2C port for an EEPROM and checks to see if the ATA connector is configured for Board Manufacturing Test Mode. AT2LP then selects an operating mode as shown below. * If an I2C EEPROM with a 0x4D4D signature is found, the CY7C68300B/CY7C68301B uses the same pinout and EEPROM format as the CY7C68300A (EZ-USB AT2). Document 38-08033 Rev. *D
* If the first two bytes of the EEPROM contain 0x534B the AT2LP uses the values stored in the EEPROM to configure the USB descriptors for normal operation. * If no EEPROM is detected, the AT2LP uses a VID/PID of 0x00/0x00. This is not a valid mode of operation. * If an invalid EEPROM signature is read, the AT2LP defaults into Board Manufacturing Test Mode. There is an additional method available to put the AT2LP into Board Manufacturing Test Mode to allow reprogramming of Page 15 of 36
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EEPROMs without an ATA/ATAPI device attached. If the ATA Reset (ARESET#) line is LOW on power-up, the AT2LP will enter Board Manufacturing Test Mode. A convenient way to pull the ARESET# line LOW is to short pins 1 and 3 on the ATA connector, which will tie the ARESET# line to the pull-down on DD7. In this mode, the AT2LP allows for reading from and writing to the EEPROM, and for board level testing through vendor specific ATAPI commands utilizing the CBW Command Block as described in the USB Mass Storage Class Bulk-Only Transport Specification. There is a vendor-specific ATAPI command for the EEPROM access (CfgCB) and one for the board level testing (MfgCB). 8.4.1 CfgCB
8.2
"No EEPROM Detected" Mode
When no EEPROM is detected at start-up, the AT2LP will enumerate with VID/PID/DID values that are all 0x00, which is not a valid mode of operation. These values can be factory programmed into the AT2LP for high-volume applications to avoid the need for an external EEPROM in some designs. Contact your local Cypress Semiconductor sales office for details.
8.3
Normal Mass Storage Mode
In Normal Mass Storage Mode, the chip behaves as a USB 2.0 to ATA/ATAPI bridge. This includes all typical USB device states (powered, configured, etc.). The USB descriptors are returned according to the values stored in the external EEPROM. An external EEPROM is required for Mass Storage Class Bulk-Only Transport compliance, since a unique serial number is required for each device. Also, Cypress requires customers to use their own Vendor and Product IDs for final products.
The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this CfgCB is shown below. Byte 0 will be a vendor-specific command designator whose value is configurable and set in the configuration data (EEPROM address 0x04). Byte 1 must be set to 0x26 to identify CfgCB. Byte 2 is reserved and must be set to zero. Byte 3 is used to determine the memory source to write/read. For the CY7C68300B/CY7C68301B, this byte must be set to 0x02, indicating the EEPROM is present. Bytes 4 and 5 are used to determine the start address. For the CY7C68300B/301B, this must always be 0x0000. Bytes 6 through 15 are reserved and must be set to zero. The data transferred to the EEPROM must be in the format specified in Table 8-6 of this data sheet. Maximum data transfer size is 255 bytes. The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW (refer to Table 8-1). The type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW (refer to Table 8-1).
8.4
Board Manufacturing Test Mode
In Board Manufacturing Test Mode, the chip behaves as a USB 2.0 device but the ATA/ATAPI interface is not fully active. Table 8-1. Command Block Wrapper
Bits Offset 0-3 4-7 8-11 (08h-0Bh) 12 (0Ch) Dir 13 (0Dh) 14 (0Eh) 15-30 (0Fh1Eh) Table 8-2. Example CfgCB Offset 0 1 2 3 4 5 6-15 CfgCB Byte Descriptions 7 bVSCBSignature (set in configuration bytes) bVSCBSubCommand (must be 0x26) Reserved (must be set to zero) Data Source (must be set to 0x02) Start Address (LSB) (must be set to zero) Start Address (MSB) (must be set to zero) Reserved (must be set to zero) 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 5 1 1 0 0 0 0 0 4 0 0 0 0 0 0 0 Bits 3 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Obsolete Reserved (0) Reserved (0) CBWCB (CfgCB or MfgCB) 7 6 5 4 dCBWTag dCBWDataTransferLength bwCBWFLAGS Reserved (0) bCBWLUN bCBWCBLength 3 2 1 0 DCBWSignature
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8.4.2 MfgCB Table 8-4. Mfg_load Data Format (continued) Byte 2 3 4 5 6 Bit(s) 7:0 7:0 7:6 5:0 7:6 5:0 7:0 DD[7:0] DD[15:8] Reserved GPIO Output Enable [5:0] Reserved GPIO Output Data [5:0] Reserved Function The mfg_load and mfg_read vendor-specific commands will be passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this MFGCB is shown below. Byte 0 is a vendor-specific command designator whose value is configurable and set in the configuration data. Byte 1 must be 0x27 to identify MfgCB. Byte 2-15 are reserved and must be set to zero. The data transfer length will be determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW. The type/direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW. Table 8-3. Example MfgCB Offset 0 1 MfgCB Byte Description 0 bVSCBSignature (set in configuration bytes) 1 bVSCBSubCommand (hardcoded 0x27) Bits 76543210 00100100 00100111
8.4.2.2 Mfg_read This USB request returns a "snapshot in time" of select AT2LP input pins. AT2LP input pins not directly associated with USB operation, can be sampled at any time during Manufacturing Test Mode operation. See Table 8-5 for an explanation of the mfg_read data format. The data length shall always be eight bytes. Table 8-5. Mfg_read Data Format Byte 0 Bit(s) 7 6 5:1 0 1 7 6 5 4 1 2 3 4 5 6 7 3 2:0 7:0 7:0 7:6 5:0 7:6 5:0 7:0 7:0 Data ARESET# (output value only) VBUS_ATA_ENABLE Reserved. This data should be ignored. INTRQ DD[15:0] Three-state Reserved. This data should be ignored. Reserved. This data should be ignored. DMARQ IORDY Reserved. This data should be ignored. DD[7:0] DD[15:8] Reserved GPIO Output Enable [5:0] Reserved GPIO Output Data [5:0] Reserved. This data should be ignored. Reserved. This data should be ignored.
2-15 2-15 Reserved (must be zero) 0 0 0 0 0 0 0 0 8.4.2.1 Mfg_load During a mfg_load, the CY7C68300B/CY7C68301B goes into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable. Normal control of the output pins are disabled. Control of the select AT2LP IO pins and their three-state controls are mapped to the ATAPI data packet associated with this request. (See Table 8-4 for an explanation of the required Mfg_load data format.) This requires a write of seven bytes. To exit Manufacturing Test Mode, a hard reset (RESET#) is required. Table 8-4. Mfg_load Data Format Byte 0 Bit(s) 7 6 5:4 3:1 0 1 7 3:6 2 1 0 ARESET# Reserved CS#[1:0] DA[2:0] Reserved DD[15:0] Three-state (0 = Hi-Z all DD pins, 1 = drive DD pins). Reserved DMACK# DIOR# DIOW# Function
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8.5 EEPROM Organization
The contents of the 256-byte (2048-bit) I2C EEPROM are arranged as follows. In Table 8-6, the column labeled "Required Contents" contains the values that must be used for proper operation of the AT2LP. The column labeled "Suggested Contents" contains suggested values for the bytes that are defined by the customer. Some values, such as the Vendor ID, Product ID and device serial number, must be customized to meet USB compliance. The "AT2LP blaster" tool on the CY4615B CD can be used to edit and program these values into an AT2LP-based product (refer to Figure 8-2). The "AT2LP primer" tool can be used to program AT2LP-based products in a manufacturing environment. See section 8.4 for details on how to use vendor-specific ATAPI commands to read and program the EEPROM. The address pins on the serial EEPROM must be set such that the EEPROM is at address 2 (A0=0, A1=1, A2=0) or address 4 (A0=0, A1=0, A2=1) for memories that are internally byteaddressed memories. Note: Devices running in Backward Compatibility Mode should use the 68300A EEPROM organization, and not the 68300B/301B/320/321 format shown in this document.
Figure 8-2. "AT2LP Blaster" Tool Screen
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Table 8-6. EEPROM Organization EEPROM Address 0x00 Field Name Field Description Required Suggested Contents Contents 0x53
AT2LP Configuration I2C EEPROM signature byte 0 I2C EEPROM signature byte 0. This byte must be 0x53. For CY7C68300A compatibility mode, these bytes should be set to 0x4D4D. I2C EEPROM signature byte 1 I2C EEPROM signature byte 1. This byte must be 0x4B APM Value ATA Device Automatic Power Management Value. If an attached ATA device supports APM and this field contains other than 0x00, the AT2LP will issue a SET_FEATURES command to Enable APM with this value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This value is ignored with ATAPI devices. Value in the first byte of the CBW CB field that designates that the CB is to be decoded as vendor specific ATA commands instead of the ATAPI command block. See section 7.0 for more detail on how this byte is used. Bits (7:6) Bit (5) Set to 1 to enable the write caching mode page (page 8). If this page is enabled, Windows will disable write caching by default which will limit write performance. Bit (4) Set to 1 to poll status register rather than waiting for INTRQ. Setting this bit to 1 will improve USB BOT test results but may introduce compatibility problems with some devices. Bit (3) Enables a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data length. This allows the CY7C68300B/CY7C68301B to work with most devices that incorrectly clear the BUSY bit before a valid status is present. Bit (2) Determines if a short packet is sent prior to the STALL of an IN endpoint. The USB Mass Storage Class Bulk-Only Specification allows a device to send a short or zero-length IN packet prior to returning a STALL handshake for certain cases. Certain host controller drivers may require a short packet prior to STALL. 1 = Force a short packet before STALL. 0 = Don't force a short packet before STALL. Bit (1) Determines if the AT2LP is to do an SRST reset during drive initialization. At least one reset must be enabled. Do not set SRST to 0 and Skip Pin Reset to 1 at the same time. 1 = Perform SRST during initialization. 0 = Don't perform SRST during initialization. Bit (0) Skip ARESET# assertion. When this bit is set, the AT2LP will bypass ARESET# during any initialization other than power up. Do not set SRST to 0 and Skip Pin Reset to 1 at the same time. 0 = Allow ARESET# assertion for all resets. 1 = Disable ARESET# assertion except for power-on reset cycles.
0x01 0x02
0x4B 0x00
0x03 0x04
Unused bVSCBSignature Value
0x80 0x24
0x05
Reserved Enable mode page 8
0x07
Disable wait for INTRQ
BUSY Bit Delay
Short Packet Before Stall
SRST Enable
Skip Pin Reset
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0x06 Field Name ATA UDMA Enable Field Description Bit (7) Enable Ultra DMA data transfer support for ATAPI devices. If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the AT2LP will utilize UDMA data transfers at the highest negotiated rate possible. 0 = Disable ATA device UDMA support. 1 = Enable ATA device UDMA support. Bit (6) Enable Ultra DMA data transfer support for ATAPI devices. If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the AT2LP will utilize UDMA data transfers at the highest negotiated rate possible. 0 = Disable ATAPI device UDMA support. 1 = Enable ATAPI device UDMA support. Bit (5:0) These bits select which UDMA modes, if supported, are enabled. Setting to 1 enables. Multiple bits may be set. The AT2LP will operate in the highest enabled UDMA mode supported by the device. The AT2LP supports UDMA modes 2, 3, and 4 only. Bit Descriptions 5 Reserved. Must be set to 0. 4 Enable UDMA mode 4. 3 Reserved. Must be set to 0. 2 Enable UDMA mode 2. 1 Reserved. Must be set to 0. 0 Reserved. Must be set to 0. Bits(7:3) Must be set to 0. Bit (2) This bit selects multi-word DMA. If this bit is set and the drive supports it, multi-word DMA is used. Bits(1:0) These bits select which PIO modes, if supported, are enabled. Setting to 1 enables. Multiple bits may be set. The AT2LP will operate in the highest enabled PIO mode supported by the device. The AT2LP supports PIO modes 0, 3, and 4 only. PIO mode 0 is always enabled by internal logic. Bit Descriptions 1 Enable PIO mode 4. 0 Enable PIO mode 3. Bit (7) Button mode. Set this bit to 1 to enable ATAPUEN, PWR500# and DRVPWRVLD to become button inputs returned on bits 2, 1, and 0 of EP1IN Bit (6) Enables a search performed at RESET to detect nonremovable ATA and ATAPI devices. Systems with only a removable device (like CF readers) will set this bit to 0. Systems with one removable device and one nonremovable device will set this bit to 1. Bit (5) Package Select. Set this bit to 1 when using the 100-pin device. 0x07 Required Suggested Contents Contents 0xD4
ATAPI UDMA Enable
UDMA Modes
0x07
Reserved Multiword DMA mode PIO Modes
0x08
Pin Configurations BUTTON_MODE
0x78
SEARCH_ATA_BUS
BIG_PACKAGE
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Table 8-6. EEPROM Organization (continued) EEPROM Address ATA_EN Field Name Field Description Bit (4) ATA sharing enable. Allows ATA bus sharing with other host devices. If ATA_EN=1 the ATA interface will be driven when VBUS_ATA_ENABLE is LOW. If ATA_EN=0 the ATA interface will be placed into Hi-Z state whenever VBUS_ATA_ENABLE is LOW. `0' = ATA signals Hi-Z when VBUS_ATA_ENABLE is LOW. `1' = ATA signals driven when VBUS_ATA_ENABLE is LOW. Bit (3) DISKRDY active polarity. `0' = Active LOW polarity. `1' = Active HIGH polarity. Bit (2) Enables GPIO2_nHS pin to indicate the current operating speed of the device (if output is enabled). `0' = Normal GPIO operation. `1' = High-speed indicator enable. Bit (1) Controls the polarity of DRVPWRVLD pin `0' = Active LOW ("connector ground" indication) `1' = Active HIGH (power indication from device) Bit (0) Enable for the DRVPWRVLD pin. When this pin is enabled, the AT2LP will enumerate a removable IDE device (normally CompactFlash) as the master device. `0' = pin disabled (most systems) `1' = pin enabled (CompactFlash systems) Bits (7:6) Must be set to zero. Bits (5:0) GPIO[5:0] Hi-Z control. `0' = Output enabled (GPIO pin is an output). `1' = Hi-Z (GPIO pin is an input). 0x00 Required Suggested Contents Contents
DISKRDY Polarity
HS Indicator Enable
Drive Power Valid Polarity
Drive Power Valid Enable
0x09
Reserved General Purpose IO Pin Output Enable
0x0A
Reserved
Bits (7:6) Must be set to zero. General Purpose IO Pin Data Bits (5:0) If the output enable bit is set, these bits select the value driven on the GPIO pins.
0x00
0x0B 0x0C
Identify Device String Pointer If this value is 00, the Identify Device data will be taken from LUN0 the device. If this string is non-zero, it is used as a pointer to Identify Device String Pointer a 24 byte ASCII (non-Unicode) string in the EEPROM. This string will be used as the device identifier. This string is used LUN1 by many operating systems as the user-visible name for the device. Delay after reset Reserved Enable CF UDMA Number of 20-ms ticks to wait between RESET and attempting to access the drive. Bits (7:4) Bit (3) `1' = Allow UDMA to be used with removable-media devices `0' = UDMA will not be used with removable-media devices Some CF devices will interfere with UDMA if the UDMA lines are connected to them. This bit tells the AT2LP if the UDMA lines are connected to the removable-media device. Bit (2) If bits 1 and 2 are both 0, the number of logical units will be determined by searching the ATA and CF buses for devices.
0x00 0x00
0x0D 0x0E
0x00 0x00
Fixed number of logical units = 2
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Table 8-6. EEPROM Organization (continued) EEPROM Address Field Name Fixed number of logical units = 1 Search ATA on VBUS removed Field Description Bit (1) If bits 1 and 2 are both 0, the number of logical units will be determined by searching the ATA and CF buses for devices. Bit (0) Search for ATA devices when VBUS returns. If this bit is set, the ATA bus will be searched for ATA devices every time AT2LP is plugged into a computer. Must be set to 0x00. Length of device descriptor in bytes. Descriptor type. USB Specification release number in BCD. Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Vendor ID. Cypress's Vendor ID may only be used for evaluation purposes, and not in released products. Product ID. Device release number in BCD LSB (product release number). Device release number in BCD MSB (silicon release number). Index to manufacturer string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Index to product string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Index to serial number string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. The USB Mass Storage Class Bulk-Only Transport Specification requires a unique serial number (in upper case, hexadecimal characters) for each device. Number of configurations supported. 1 for mass storage: 2 for HID: 3 for CSM Length of device descriptor in bytes. Type Descriptor type. USB Specification release number in BCD. USB Specification release number in BCD. Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Number of configurations supported. 0x0A 0x06 0x00 0x02 0x00 0x00 0x00 0x40 0x01 0x00 0x12 0x01 0x00 0x02 0x00 0x00 0x00 0x40 Your Vendor ID Your Product ID Your release number 0x53 Required Suggested Contents Contents
0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E
Reserved bLength bDescriptor Type bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB) bcdDevice (MSB) iManufacturer
Device Descriptor
0x1F
iProduct
0x69
0x20
iSerialNumber
0x75
0x21
bNumConfigurations
0x03
Device Qualifier 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A bLength bDescriptor bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 bNumConfigurations
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 Field Name bReserved bLength bDescriptorType bTotalLength (LSB) bTotalLength (MSB) bNumInterfaces bConfiguration Value iConfiguration Field Description Reserved for future use. Must be set to zero. Length of configuration descriptor in bytes. Descriptor type. Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors. Number of interfaces supported. The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x01. Index to the configuration string. This entry must equal half of the address value where the string starts, or 0x00 if the string does not exist. Device attributes for this configuration. Bit (7) Reserved. Must be set to 1. Bit (6) Self-powered. Must be set to 1. Bit (5) Remote wake-up. Must be set to 0. Bits (4-0) Reserved. Must be set to 0. Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). 0x00 reported for self-powered devices. Note: A value of 0x00 or 0x01 results in the 56-pin package configuring itself for self-powered mode, whereas a value greater than 0x01 results in the 56-pin package reporting itself as bus-powered. This is regardless of what address 0x33 is set to reflect in the 56-pin package. Interface and Endpoint Descriptors Interface Descriptor 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Length of interface descriptor in bytes. Descriptor type. Interface number. Alternate setting. Number of endpoints. Interface class. Interface subclass. Interface protocol. Index to first interface string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. Length of this descriptor in bytes. Endpoint descriptor type. This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size. To be set by speed (Full speed 0x0040; High speed 0x0200) High-speed interval for polling (maximum NAK rate). Set to zero for full speed. 0x00 0x07 0x05 0x02 0x02 0x00 0x02 0x50 0x00 0x09 0x04 0x00 0x00 0x02 0x08 0x06 0xC0 0x01 0x00 Required Suggested Contents Contents 0x00 0x09 0x02 0x20 0x00 0x01
Configuration Descriptor
0x33
bmAttributes
0x34
bMaxPower
0x01
USB Bulk Out Endpoint 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval Field Name Field Description Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 8. This is a bulk endpoint. Max data transfer size. Automatically set by AT2 (Full speed 0x0040; High speed 0x0200) High-speed interval for polling (maximum NAK rate). Set to zero for full speed. Length of HID interface descriptor Interface descriptor type Number of interfaces (2) Alternate setting Number of endpoints used by this interface Class code Sub class sub sub class Index of string descriptor Length of this descriptor in bytes. Endpoint descriptor type. This is an In endpoint, endpoint number 1. This is an interrupt endpoint. Max data transfer size. Interval for polling (max. NAK rate). Length of HID descriptor Descriptor Type HID HID Class Specification release number (1.10) Country Code Number of class descriptors (1 report descriptor) Descriptor Type Length of HID report descriptor 0x09 0x21 0x10 0x01 0x00 0x01 0x22 0x22 0x00 0x00 Vendor defined - FFA0 0x06 0xA0 0xFF 0x00 Required Suggested Contents Contents 0x07 0x05 0x88 0x02 0x00 0x02
USB Bulk In Endpoint
(Optional) HID Interface Descriptor 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x65 0x66 0x67 0x68 bLength bDescriptorTypes bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceSubSubClass iInterface bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval bLength bDescriptorType bcdHID (LSB) bcdHID (MSB) bCountryCode bNumDescriptors bDescriptorType wDescriptorLength (LSB) wDescriptorLength (MSB) Terminator Usage_Page 0x09 0x04 0x02 0x00 0x01 0x03 0x00 0x00 0x00 0x07 0x05 0x81 0x03 0x02 0x00 0x10
USB Interrupt In Endpoint
(Optional) HID Descriptor
Terminator Descriptors (Optional) HID Report Descriptor
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0x69 0x6A 0x6B 0x6C 0x6D 0x6E Input Report 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A Output Report 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface End Collection Byte length of this descriptor Interface Descriptor type Number of interface. Value used to select an alternate setting for the interface identified in prior field Number of endpoints used by this interface (excluding endpoint 0) that are CSM dependent Must be set to zero Must be set to zero Index of a string descriptor that describes this Interface 0x02 0x0D 0x00 0x00 (optional) Standard Content Security Interface Descriptor 0x09 0x0D 0x02 Output Output (Data, Variable, Absolute Report_Count Report Count 2 fields Report_Size Report Size 8 bits Logical_Maximum Logical Maximum (127) Logical_Minimum Logical Minimum (-128) Usage Usage - vendor defined 0x09 0xA9 0x15 0x80 0x25 0x7F 0x75 0x08 0x95 0x02 0x91 0x02 0xC0 Input Input (Data, Variable, Absolute) Report_Count 2 fields Report_Size 8 bits Logical_Maximum 127 Logical_Minimum -128 Usage Vendor defined 0x09 0xA7 0x15 0x80 0x25 0x7F 0x75 0x08 0x95 0x02 0x81 0x02 Usage Vendor defined Collection Application Usage Field Name Vendor defined Field Description Required Suggested Contents Contents 0x09 0xA5 0xA1 0x01 0x09 0xA6
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0x91 0x92 0x93 0x94 0x95 bLength bDescriptorType bChannelID bmAttributes Field Name Field Description Byte length of this descriptor channel descriptor type Number of the channel, must be a zero based value that is unique across the device Bits(7:5) Must be set to 0. Bit (4:0) 0 = Not used 1 = Interface 2 = Endpoint 3...31 = Reserved values bRecipient Identifier of the target recipient If Recipient type field of bmAttributes = 1 then bRecipient field is the bInterfaceNumber If Recipient type field of bmAttributes = 2 then bRecipient field is an endpoint address, where: D7: Direction (0 = Out, 1 = IN) D6...D4: reserved and set to zero D3...D0: Endpoint number alternate setting for the interface to which this channel applies Recipient Logical Unit Index of a class-specific CSM descriptor That describes one of the Content Security Methods (CSM) offered by the device CSM Variant descriptor Byte length of this descriptor CSM Descriptor type Index of a class-specific CSM descriptor that describes on of the Content Security Methods offered by the device. Index of string descriptor that describes the Content Security Method CSM Descriptor Version number 0x10 0x02 0x00 LANGID string descriptor length in bytes. Descriptor type. Language supported. The CY7C68300B supports one LANGID value. 0x04 0x03 0x09 0x04 0x2C 0x03 "C" 0x43 0x00 "y" 0x79 0x00 Page 26 of 36 0x06 0x23 0x01 0x00 Required Suggested Contents Contents 0x09 0x22
Channel Descriptor
0x96
0x97 0x98 0x99
bRecipientAlt bRecipientLogicalUnit bMethod
0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB
bMethodVariant bLength bDescriptorType bMethodID iCSMDescriptor bcdVersion (LSB) bcsVersion (MSB) Terminator bLength bDescriptorType LANGID (LSB) LANGID (MSB) bLength bDescriptorType bString bString bString bString
CSM Descriptor
USB String Descriptor-Index 0 (LANGID)
USB String Descriptor-Manufacturer String descriptor length in bytes (including bLength). Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB.
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bLength bDescriptorType bString bString bString Field Name Field Description Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. String descriptor length in bytes (including bLength). Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. 0x03 "U" 0x55 0x00 "S" 0x53 Page 27 of 36 Required Suggested Contents Contents "p" 0x70 0x00 "r" 0x72 0x00 "e" 0x65 0x00 "s" 0x73 0x00 "s" 0x73 0x00 " " 0x20 0x00 "S" 0x53 0x00 "e" 0x65 0x00 "m" 0x6D 0x00 "i" 0x69 0x00 "c" 0x63 0x00 "o" 0x6F 0x00 "n" 0x6E 0x00 "d" 0x64 0x00 "u" 0x75 0x00 "c" 0x63 0x00 "t" 0x74 0x00 "o" 0x6F 0x00 "r" 0x72 0x00 0x2C
USB String Descriptor-Product
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString Field Name Field Description Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Required Suggested Contents Contents 0x00 "B" 0x42 0x00 "2" 0x32 0x00 "." 0x2E 0x00 "0" 0x30 0x00 " " 0x20 0x00 "D" 0x53 0x00 "i" 0x74 0x00 "s" 0x6F 0x00 "k" 0x72 0x00
USB String Descriptor-Serial Number (Note: The USB Mass Storage Class specification requires a unique serial number in each device. Not providing a unique serial number can cause the operating system to crash. The serial number must be at least 12 characters, but some USB hosts will only treat the last 12 characters of the serial number as unique.) 0xEA 0XEB 0XEC 0XED 0XEE 0XEF 0XF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF bLength bDescriptor Type bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString String descriptor length in bytes (including bLength). Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. 0x03 "1" 0x31 0x00 "2" 0x32 0x00 "3" 0x33 0x00 "4" 0x34 0x00 "5" 0x35 0x00 "6" 0x36 0x00 "7" 0x37 0x00 "8" 0x38 0x00 "9" 0x39 0x00 "0" 0x30 0x00 0x22
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Table 8-6. EEPROM Organization (continued) EEPROM Address 0X100 0X101 0X102 0X103 bString bString bString bString Field Name Field Description Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Required Suggested Contents Contents "A" 0x41 0x00 "B" 0x42 0x00
Identify Device String (Note: This is not a Unicode string. It is the ASCII string returned by the device in the Identify Device information. It is a fixed length (24 bytes). Changing this string may cause CD authoring software to incorrectly identify the device.) 0X104 0X105 0X106 0X107 0X108 0X109 0X10A 0X10B 0X10C 0X10D 0X10E 0X10F 0X110 0X111 0X112 0X113 0X114 0X115 0X116 0X117 0X118 0X119 0X11A 0X11B 0x11C to 0x1FF Device name byte 1 Device name byte 2 Device name byte 3 Device name byte 4 Device name byte 5 Device name byte 6 Device name byte 7 Device name byte 8 Device name byte 9 Device name byte 10 Device name byte 11 Device name byte 12 Device name byte 13 Device name byte 14 Device name byte 15 Device name byte 16 Device name byte 17 Device name byte 18 Device name byte 19 Device name byte 20 Device name byte 21 Device name byte 22 Device name byte 23 Device name byte 24 Unused ROM Space ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character Amount of unused ROM space will vary depending on strings. "C" 0x43 "y" 0x79 "p" 0x70 "r" 0x72 "e" 0x65 "s" 0x73 "s" 0x73 " " 0x20 "C" 0x43 "u" 0x75 "s" 0x73 "t" 0x74 "o" 0x6f "m" 0x6d " " 0x20 "N" 0x4e "a" 0x61 "m" 0x6d "e" 0x65 " " 0x20 "L" 0x4c "U" 0x55 "N" 0x4e "0" 0x30 0xFF
Note: More than 0X100 bytes of configuration are shown for example only. AT2LP only supports 0X100 total bytes.
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Table 8-7. EEPROM-related Vendor-specific Commands Label LOAD_CONFIG_DATA READ_CONFIG_DATA bmRequestType bRequest 0x40 0xC0 0x01 0x02 wValue 0x0000 Data Source wIndex 30x02 - 0x0F wLength Data Length Data Configuration Data Configuration Data
Starting Address Data Length
8.6
Programming the EEPROM
There are three methods to program the EEPROM: * External device programmer * USB commands listed in Table 8-7 * In-system programming on a bed-of-nails tester. Any vendor-specific USB write request to the Serial ROM device configuration space will simultaneously update internal configuration register values as well. If the I2C device is programmed without vendor specific USB commands, AT2LP must be synchronously reset (RESET#) before configuration data is reloaded. The AT2LP supports a subset of the "slow mode" specification (100 KHz) required for 24LCXXB EEPROM family device support. Features such as "Multi-Master," "Clock Synchronization" (the SCL pin is output only), "10-bit addressing," and "CBUS device support" are not supported. Vendor-specific USB commands allow the AT2LP to address up to 256 bytes of data. 8.6.1 LOAD_CONFIG_DATA
address specified by the wIndex field. The wLength field denotes the length in bytes of data requested from the data source. Legal values for wValue are as follows: * 0x0000 Configuration bytes, addresses 0x0 - 0xF only * 0x0002 External I2C memory device Illegal values for wValue will result in undefined operation. Attempted reads from an I2C memory device when none is connected will result in undefined operation. Attempts to read configuration bytes with starting addresses greater than 0xF will also result in undefined operation.
9.0
Absolute Maximum Ratings
Storage Temperature.................................. -65C to +150C Ambient Temperature with Power Supplied ..... 0C to +70C Supply Voltage to Ground Potential .............-0.5 V to +4.0 V DC Input Voltage to Any Input Pin ............................... 5.25 V DC Voltage Applied to Outputs in Hi-Z State......................................... -0.5 V to VCC + 0.5 V Power Dissipation..................................................... 300 mW Static Discharge Voltage.......................................... > 2000 V Max Output Current Per I/O Port (D0-D7, D8-15, ATA control)........................................ 10 mA
This request enables configuration data writes to the AT2LP's configuration space. The wIndex field specifies the starting address and the wLength field denotes the data length in bytes. Legal values for wValue are as follows: * 0x0000 Configuration bytes, address range 0x2 - 0xF * 0x0002 External I2C memory device Configuration-byte writes must be constrained to addresses 0x2 through 0xF, as shown in Table 8-7. Attempts to write outside this address space will result in undefined operation. Configuration-byte writes only overwrite AT2LP Configuration Byte registers, the original data source (I2C memory device) remains unchanged. 8.6.2 READ_CONFIG_DATA
10.0
Operating Conditions
TA (Ambient Temperature Under Bias) ............. 0C to +70C Supply Voltage ...........................................+3.15V to +3.45V Ground Voltage ................................................................. 0V Fosc (Oscillator or Crystal Frequency) .... 24 MHz 100 ppm, .................................................................. Parallel Resonant
This USB request allows data retrieval from the data source specified by the wValue field. Data is retrieved beginning at the
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11.0
VCC VCC Ramp VIH VIL II VIH_X VIL_X VOH VOL IOH IOL CIN ISUSP
DC Characteristics
Description Supply Voltage Supply Ramp-up 0V to 3.3V Input High Voltage Input Low Voltage Input Leakage Current Crystal Input HIGH Voltage Crystal Input LOW Voltage Output Voltage High Output Voltage Low Output Current High Output Current Low Input Pin Capacitance Suspend Current CY7C68300B/CY7C68320 Suspend Current CY7C68301B/CY7C68321 All but D+/D- D+/D- Connected: Disconnected: Connected: Disconnected: USB High Speed: USB Full Speed: Current before device is granted full current requested in bMaxPower VCC > 3.0V 5.0 200 0.5 0.3 300 100 50 35 43 IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 1.2 1.0 380 150 85 65 0 < VIH < VCC 2 -0.5 Conditions Min. 3.15 200 2 -0.5 5.25 0.8 10 Typ. 3.3 Max. 3.45 Unit V s V V A 5.25 0.8 V V mA mA pF pF mA mA A A mA mA mA ms s
Parameter
ICC IUNCONFIG TRESET
Supply Current Unconfigured Current Reset Time After Valid Power Pin Reset After Power-Up
12.0 AC Electrical Characteristics
12.1 USB Transceiver
Complies with the USB 2.0 specification.
12.2 ATA Timing
The ATA interface supports ATA PIO modes 0, 3, and 4, Ultra DMA modes 2, 3, and 4, and multiword DMA mode 2 per the ATA/ATAPI 6 Specification. The AT2LP will select the highest common transfer rate.
13.0 Ordering Information
Part Number CY7C68300B-56PVXC CY7C68301B-56PVXC CY7C68300B-56LFXC CY7C68301B-56LFXC CY7C68320-56LFXC CY7C68321-56LFXC CY7C68320-100AXC CY7C68321-100AXC CY4615B Package Type 56 SSOP Lead-free for self- and bus-powered designs 56 SSOP Lead-free for battery-powered designs 56 QFN Lead-free for self- and bus-powered designs 56 QFN Lead-free for battery-powered designs 56 QFN Lead-free for self- and bus-powered designs 56 QFN Lead-free for battery-powered designs 100 TQFP Lead-free for self- and bus-powered designs 100 TQFP Lead-free for battery-powered designs EZ-USB AT2LP Reference Design Kit GPIO Pins - - - - 3[4] 3[4] 6 6 n/a
Note: 4. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321.
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14.0 Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Figure 14-1. 100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)
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14.0 Package Diagrams (continued)
Figure 14-2. 56-lead Shrunk Small Outline Package 056
51-85062-*C
TOP VIEW
SIDE VIEW
0.08[0.003] C
BOTTOM VIEW
A
7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1
1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
0.80[0.031] DIA.
2
E-PAD
7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319]
(PAD SIZE VARY BY DEVICE TYPE)
0.30[0.012] 0.50[0.020]
0-12
0.50[0.020] C 6.45[0.254] 6.55[0.258]
0.24[0.009] 0.60[0.024]
(4X)
Dimensions are in millimeters
SEATING PLANE
Figure 14-3. 56-Lead QFN 8 x 8 mm LF56A
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15.0 PCB Layout Recommendations
The following recommendations should be followed to ensure reliable high-performance operation. * At least a four-layer impedance controlled board is required to maintain signal quality. * Specify impedance targets (ask your board vendor what they can achieve). * To control impedance, maintain uniform trace widths and trace spacing. * To minimize reflected signals, minimize the number of stubs. * Connections between the USB connector shell and signal ground must be done near the USB connector. * Use bypass/flyback capacitors on VBus near the connector. * DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20 - 30 mm. * Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. * For a more stable design, do not place vias on the DPLUS or DMINUS trace routing. * Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. * Source for recommendations: * EZ-USB FX2 PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf. * High-speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
16.0 Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the AT2LP through the device's metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of vias. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note Surface Mount Assembly of AMKOR's MicroLeadFrame (MLF) Technology. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 16-1 displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that "No Clean," type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Figure 16-2 is a plot of the solder mask pattern and Figure 163 displays an X-Ray image of the assembly (darker areas indicate solder.)
0.017" dia Solder Mask Cu Fill Cu Fill
PCB Material
0.013" dia
PCB Material
Via hole for thermally connecting the QFN to the circuit board ground plane.
This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane
Figure 16-1. Cross-Section of the Area Under the QFN Package
Figure 16-2. Plot of the Solder Mask (White Area) Document 38-08033 Rev. *D Page 34 of 36
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Figure 16-3. X-ray Image of the Assembly
17.0
Other Design Considerations
Certain design considerations must be followed to ensure proper operation of the CY7C68300B/CY7C68301B. The following items should be taken into account when designing a USB device with the CY7C68300B/CY7C68301B.
ensure that devices have large enough buffers to handle the flow of data to/from the drive. The exact buffer size needed depends on a number of variables, but a good rule of thumb is:
(aprox min buffer) = (data rate) * (seek time + rotation time + other)
17.1
Proper Power-up Sequence
Power must be applied to the CY7C68300B/CY7C68301B before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300B/CY7C68301B will start up in an undefined state. Designs that utilize separate power supplies for the CY7C68300B/CY7C68301B and the ATA/ATAPI device are not recommended.
where other may include things like time to switch heads, power-up a laser, etc. Devices with buffers that are too small to handle the extra data may perform considerably slower than expected.
18.0
Disclaimers, Trademarks, and Copyrights
17.2
IDE Removable Media Devices
The CY7C68300B/CY7C68301B does not fully support IDE removable media devices. Changes in media state are not reported to the operating system so users will be unable to eject/reinsert media properly. This may result in lost or corrupted data.
17.3
Devices With Small Buffers
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. Microsoft and Windows are registered trademarks of Microsoft Corporation. Apple and Mac OS are registered trademarks of Apple Computer, Inc. EZ-USB AT2LP, EZ-USB AT2, EZ-USB FX2 and EZ-USB TX2 are trademarks, and EZ-USB is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
The size of the ATA/ATAPI device's buffer can greatly affect the overall data transfer performance. Care should be taken to
Document 38-08033 Rev. *D
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
CY7C68300B/CY7C68301B CY7C68320/CY7C68321
Document History Page
Description Title: CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge Document Number: 38-08033 REV. ** *A *B *C *D ECN NO. 129739 215125 274109 318133 323408 Issue Date 12/04/03 SEE ECN SEE ECN SEE ECN SEE ECN Orig. of Change GIR KKU ARI GIR GIR New data sheet Added HID descriptor, Content Security Methods descriptor, alternate functions on 3 pins, and alternate EEPROM addressing Incorporated CY7C68320 information. Updated graphics to reflect this change Incorporated CY7C68301B and CY7C68321 information. Updated graphics to reflect this change. Revised data for final release and posting to website. Swapped the part numbers in the DC Characteristics table to match their correct ISUSP values. Description of Change
Document 38-08033 Rev. *D
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